Non-volatile memory integrated circuits are well known in the art. One type of a non-volatile memory cell structure is a NAND structure, which is shown in FIG. 1B. Such a structure is described in U.S. Pat. Nos. 4,959,812 and 5,050,125 whose disclosures are incorporated herein in their entirety. In this type of structure, the NAND string comprises a plurality of serially connected non-volatile floating gate memory cells, each with a control gate. At the ends of the NAND structure are two select transistor (SG0 and SGn). Each select transistor has a gate and serves to pass the programming voltage supplied to either the drain/source of the select transistor to the plurality of serially connected NAND memory cells.
Another type of NAND structure is that shown in FIG. 1A. Such a structure is described in U.S. Pat. No. 6,885,586 whose disclosure is also incorporated herein in its entirety. In this structure, each floating gate memory cell has an associated select transistor. A current limited transistor provides the current to one end of the select transistor located at one end of the NAND structure.
In either of the NAND structures shown in FIGS. 1A and 1B, controlling the programming current as well as programming speed is crucial, because of the variation in the bit line voltage due to the biasing voltage applied to the select transistor at one end of the NAND structure.